CST Microwave Studio
Robin Cedeno
Signal Integrity Engineer
Summary
Signal and Power Integrity Engineer with over 17 years experience on ATE designs, simulation and measurement. Very good engineering principles, theories, specifications, and standards. PCB and Simulations experienced, 2000+ RF - HS designs for the most important high tech companies.
Overview
24
24
years of professional experience
2
2
Languages
Work History
Signal & Power Integrity Engineering Manager
PTSL
12.2022 - Current
Signal & Power Integrity Manager
RDAltanova
06.2008 - 11.2022
Field Service Engineer for ATE Testers
Intel
04.2003 - 06.2008
ATE Engineer
Teradyne
01.2001 - 04.2003
Education
Bachelor of Science - Electronics
Instituto Tecnologico Costa Rica
05.2001 -
Skills
High Speed & RF Designs (400 Gbps - 100 GHz)
MLO Design
Probe Head Design
Socket (Coax, Plastic, Ceramic) Design
Interposer Design
Design DFM-DFA-DFT
Patent:
1.0 MICROSTRIP CONTACTOR WITH SHARED COMMON GROUND
U.S. Application Serial No. 63/468,868
Detail: Probe for High Speed Measurements
2.0 MICROSTRIP CONTACTOR FOR A TEST ASSEMBLY
U.S. Application Serial No. 18/675,683
Detail: Probe for High Speed Measurements
Software
HFFS
Power SI from Sigrity
Power DC from Sigrity
Allegro Cadence
www.linkedin.com/in/robin-cedeno-a2
Timeline
Signal & Power Integrity Engineering Manager
PTSL
12.2022 - Current
Signal & Power Integrity Manager
RDAltanova
06.2008 - 11.2022
Field Service Engineer for ATE Testers
Intel
04.2003 - 06.2008
Bachelor of Science - Electronics
Instituto Tecnologico Costa Rica
05.2001 -
ATE Engineer
Teradyne
01.2001 - 04.2003
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